1. Technical Field
The present invention generally relates to methods for making a semiconductor device and, more particularly, to methods for a semiconductor device using a flowable oxide film.
2. Description of Related Art
Various processes for forming metal lines and contacts in semiconductor devices have been developed. In some cases, a metal film is deposited and then etched. In other cases, a so-called damascene process is utilized. A "damascene" process is a process in which a trench or an opening is formed in an insulating film and then filled in with a conductive material. The conductive material is then planarized. A "dual damascene" process involves the simultaneous fabrication of a conductive contact and a conductive wiring. Specifically, in a dual damascene process, a contact hole is formed in an insulating film such as a TEOS film and then a trench for the wiring is formed in the insulating film by widening an upper portion of the contact hole. A conductive material is then deposited on the insulating film and to fill in the contact hole and the trench. The deposited conductive material is then planarized by a planarization process such as chemical mechanical polishing (CMP) using the insulating film as a stopper. Such a dual damascene process reduces the number of process steps and eliminates an interface between the conductive contact and the conductive wiring.
Some steps of a conventional dual damascene process are shown in FIGS. 1(a)-1(d). With reference to FIG. 1(a), a contact hole 18 is formed in an insulating film 16 such as a TEOS film and exposes a portion of the upper surface of a conductive line 14 formed in an insulating layer 12. Next, as shown in FIG. 1(b), an antirefiective coating (ARC) film 20 is deposited and a resist 22 is formed on ARC film 20. As can be seen in FIG. 1(b), due to the topography of the upper surface of ARC film 20 caused by contact -hole 18, resist 22 has a variable thickness. Resist 22 is selectively exposed and developed to provide a patterned resist layer as shown in FIG. 1(c). A reactive ion etching (RIE) process is then used to etch ARC film 20 and TEOS layer 16 using the patterned resist as a mask. ARC film 20 and TEOS film 16 have different etching rates. If, during this RIE process, the ARC film 20 is etched at a faster rate than TEOS film 16, conductive line 14 may be damaged. On the other hand, if during this RIE process, ARC film 20 is etched at a slower rate than TEOS film 16, a structure like that shown in FIG. 1(d) has been found to remain after the RIE process. After the removal of the remaining resist 22 and ARC film 20, TEOS spikes 24 adjacent to the contact hole/trench boundary remain. An adhesion/barrier film of, for example, titanium nitride is then deposited on the surface of TEOS film 16 and on the sidewalls and bottom walls of the contact hole and trench. However, in the regions of TEOS spikes 24, the adhesion/barrier film is unevenly deposited and, in some areas, may not be deposited at all. Thus, in a subsequent step during which a conductive material such as tungsten is sputtered or deposited in the contact hole and trench, voids in the tungsten can occur in regions where the adhesion/barrier layer is not present. This can lead to discontinuities and increased resistance of the contacts and lines formed by the tungsten. In addition, with reference to FIG. 1(b), the varying thickness of resist 22 adversely impacts the lithography process and contributes to the difficulty in forming trenches having highly accurate dimensions. Similar problems occur if ARC film 20 is omitted and resist 22 is deposited on the upper surface of TEOS layer 16 and to fill in contact hole 18.